The present invention relates generally to the semiconductor integrated circuits and more particularly to an apparatus and method that provides for single and multiple device dicing options for random access memories (RAMs).
The manufacture of integrated circuits (ICs) typically begins with the formation of active devices in a semiconductor wafer substrate, followed by the interconnection of the active devices with one or more patterned conductive (wiring) layers. The ICs are usually separated by from one another on the surface of the wafer by perpendicular lanes (called xe2x80x9cstreets,xe2x80x9d xe2x80x9csaw lanesxe2x80x9d or xe2x80x9cscribe linesxe2x80x9d). The scribe lines indicate where the wafer will be cut to produce individual ICs.
It is known in the prior art to provide test circuits or other expendable structures in the scribe lines that come into contact with the ICs themselves. For example, U.S. Pat. No. 5,059,899 issued to Farnsworth et al. on Oct. 22, 1991 discloses test bond pads and/or circuitry, disposed within the scribe lines of a wafer, that are coupled to ICs by interconnecting lines. When the wafer is cut, the interconnecting lines are severed.
Prior to cutting the wafer, each IC is tested for some level of functionality. Failing ICs are typically identified by an ink mark. The wafer is then cut (usually with a saw) along the scribe lines to produce rectangular sections containing one IC (called slices or dies). In order to eliminate lifting of layers during the sawing the process, and to ensure that contaminants do not subsequently migrate into the active areas of the IC, guard rings or guard walls run along the periphery of each IC. U.S. Pat. No. 5,270,256 issued to Bost et al. on Dec. 14, 1993 discloses a method of forming a guard wall around the edge of an integrated circuit to prevent delamination effects. Functional dies are placed into circuit packages and electrically connected to package leads by bond wires connected at one end to bond pads on the IC and at the other end to the package leads.
It is also desirable to provide ICs that can be adjusted between two or more operational modes. Such multi-mode ICs can be manufactured en masse, and subsequently configured according to current demands. Unfortunately, once the last wiring layers have been patterned on the wafer, the IC is essentially complete and little variation can be introduced into the IC""s functionality without resorting to complex manufacturing processes and/or additional circuitry.
It is known in the prior art to provide memory devices having adjustable data input/output (I/O) widths. A mode circuit is provided that is responsive to a number of control signals. In response to a particular signal or sequence of signals, the type of I/O configuration may be altered. For example, a 16 Megabit (Mb) DRAM can have a default configuration of a sixteen bit I/O (1Mxc3x9716) and be subsequently programmed to an eight bit I/O (2Mxc3x978). The drawback of such approaches is the additional circuit complexity and die area that are required to implement such programmable mode options.
It is also known in the prior art to use the initial portion of the fabrication process to create a number of circuits having standard functions, and then to wire the standard circuits with one or more custom wiring layers to produce an IC having a custom function. The standard circuits can vary from very complex circuits, selected from a standard library of circuit blocks, to more basic circuits, such as individual logic gates. In order to minimize wasted die area in such custom or semi-custom approaches, it is known to dispense with scribe lines, and to cut through active device areas.
U.S. Pat. No. 5,016,080 issued to Piccolo T. Giannella on May 14, 1991 discloses a method of fabricating semi-custom circuits in which a number of isolated circuit cells are formed on a wafer with scribe lines being provided in only one direction. Groups of adjacent cells are joined by a custom metallization layer to form semi-custom integrated circuits. The wafer is cut along the pre-formed scribe line in one direction and in the second direction according to the semi-custom IC boundaries. The isolation of each circuit cell ensures contamination does not adversely effect the semi-custom ICs.
U.S. Pat. No. 5,217,916 issued to Anderson et al. on Jun. 8, 1993 discloses a method of fabricating application specific integrated circuits in which a wafer is sliced in one direction along saw lanes, and in another (perpendicular) direction, along a rows of transistors.
It is an object of the present invention to provide a semiconductor device having a stand-alone mode, wherein the integrated circuit provides an output in response to a set of inputs, and a multi-device mode, wherein one or more integrated circuits receive a set of inputs and provide a number of outputs.
It is another object of the present invention to provide a method of manufacturing semiconductor devices having single device and multi-device modes of operation, wherein the mode of operation is determined at the assembly stage.
It is yet another object of the present invention to provide a semiconductor RAM device having a data I/O width that is configurable after devices have been manufactured on a semiconductor wafer.
According to the present invention, a number of integrated circuits are fabricated on a semiconductor wafer. Adjacent integrated circuits are coupled by an interconnect scheme that allows signals received from one integrated circuit to be used by one or more adjacent integrated circuits. If single integrated circuit devices are desired, the wafer is diced into single integrated circuits, and the integrated circuits are placed in a single device mode. If a devices composed of multiple integrated circuits are desired, the wafer is diced into groups of multiple integrated circuits, and the integrated circuits placed in a multiple device mode.
According to one aspect of the present invention, the devices are placed in the single device mode by dicing the wafer into single integrated circuits and cutting through the interconnect schemes.
According to another aspect of the present invention the interconnect scheme connecting adjacent integrated circuits includes an underpass or overpass structure to prevent lifting of the integrated circuit layers during the wafer cutting step of the assembly process.
According to another aspect of the present invention the integrated circuits are RAM devices and the interconnect scheme couples a portion of input addresses from one RAM device to an adjacent RAM device.
According to another aspect of the invention the data I/O width of RAM devices may be increased by adjacent RAM devices providing data I/Os in response to the same address.
An advantage of the present invention is that semiconductor RAM devices may be manufactured as uniform devices on a wafer, and then subsequently diced into multiple device integrated circuits to produce larger I/O width devices.
Other objects and advantages of the present invention will become apparent in light of the following description thereof.